| MPSoC Project Status | |||
| Project File: | MPSoC.ise | Current State: | Programming File Generated |
| Module Name: | MPSoC_top |
|
No Errors |
| Target Device: | xc2vp30-7ff896 |
|
399 Warnings |
| Product Version: | ISE 10.1.03 - Foundation Simulator |
|
All Signals Completely Routed |
| Design Goal: | Balanced |
|
All Constraints Met |
| Design Strategy: | Xilinx Default (unlocked) |
|
0 (Timing Report) |
| MPSoC Partition Summary | [-] | |||
| No partition information was found. | ||||
| Device Utilization Summary | [-] | ||||
| Logic Utilization | Used | Available | Utilization | Note(s) | |
| Total Number Slice Registers | 8,475 | 27,392 | 30% | ||
| Number used as Flip Flops | 8,459 | ||||
| Number used as Latches | 16 | ||||
| Number of 4 input LUTs | 14,728 | 27,392 | 53% | ||
| Logic Distribution | |||||
| Number of occupied Slices | 12,416 | 13,696 | 90% | ||
| Number of Slices containing only related logic | 12,416 | 12,416 | 100% | ||
| Number of Slices containing unrelated logic | 0 | 12,416 | 0% | ||
| Total Number of 4 input LUTs | 20,551 | 27,392 | 75% | ||
| Number used as logic | 14,728 | ||||
| Number used as a route-thru | 4,203 | ||||
| Number used for Dual Port RAMs | 1,536 | ||||
| Number used as Shift registers | 84 | ||||
| Number of bonded IOBs | |||||
| Number of bonded | 21 | 556 | 3% | ||
| IOB Flip Flops | 15 | ||||
| Number of PPC405s | 0 | 2 | 0% | ||
| Number of Tbufs | 64 | 6,848 | 1% | ||
| Number of Block RAMs | 112 | 136 | 82% | ||
| Number of MULT18X18s | 16 | 136 | 11% | ||
| Number of GCLKs | 4 | 16 | 25% | ||
| Number of DCMs | 1 | 8 | 12% | ||
| Number of BSCANs | 1 | 1 | 100% | ||
| Number of GTs | 0 | 8 | 0% | ||
| Number of GT10s | 0 | 0 | 0% | ||
| Total equivalent gate count for design | 7,804,743 | ||||
| Additional JTAG gate count for IOBs | 1,008 | ||||
| Performance Summary | [-] | |||
| Final Timing Score: | 0 | Pinout Data: | Pinout Report | |
| Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
| Timing Constraints: | All Constraints Met | |||
| Clock Report | [-] | |||||
| Clock Net | Resource | Locked | Fanout | Net Skew(ns) | Max Delay(ns) | |
| Inst_Multiprocs/dlmb | ||||||
| _cntlr_1_BRAM_PORT_B | ||||||
| RAM_Clk | BUFGMUX4S | No | 4663 | 0.268 | 1.258 | |
| clk_IBUFG | BUFGMUX0P | No | 2007 | 0.263 | 1.245 | |
| CLK_DIVIDE_I/clk_sta | ||||||
| te | BUFGMUX7P | No | 91 | 0.247 | 1.240 | |
| Inst_Multiprocs/DBG_ | ||||||
| CLK_s | BUFGMUX2P | No | 122 | 0.169 | 1.247 | |
| GLB_MEM_I/data_and00 | ||||||
| 00_inv | Local | 29 | 0.291 | 2.334 | ||
| Inst_Multiprocs/debu | ||||||
| g_module/bscan_updat | ||||||
| e | Local | 1 | 0.000 | 0.356 | ||
| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | Current | Wed May 13 21:45:18 2009 | 0 | 383 Warnings | 236 Infos | |
| Translation Report | Current | Wed May 13 21:45:40 2009 | 0 | 1 Warning | 68 Infos | |
| Map Report | Current | Wed May 13 21:46:24 2009 | 0 | 12 Warnings | 3 Infos | |
| Place and Route Report | Current | Wed May 13 22:02:00 2009 | 0 | 3 Warnings | 3 Infos | |
| Static Timing Report | Current | Wed May 13 22:02:40 2009 | 0 | 0 | 3 Infos | |
| Bitgen Report | Current | Wed May 13 22:03:46 2009 | 0 | 1 Warning | 0 | |